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WB1215
Serial Input PLL with 1.2-GHz Prescaler
Features
* Operating voltage 2.7V to 5.5V * Operating frequency: up to 1.2 GHz with prescaler ratios of 64/65 and 128/129 * Lock detect feature * Power-down mode * 20-pin TSSOP (Thin Shrink Small Outline Package)
Applications
* * * * Wireless LAN Wireless communication handsets Base Stations Microcells
WB1215 PLL Block Diagram
GND (7) VCC (5) VP (4)
(6) FIN (10) Prescaler 64/65 or 128/129 Binary 7-Bit Swallow Counter
Binary 11-Bit Programmable Counter
fp
DO
Phase Detector
Charge Pump
(16) BISW (15) FC (20) r (18) p
18-Bit Latch OSC_IN OSC_OUT (1) 14-Bit Reference Counter (3) fr
(8) LD
LE
(14)
Latch Selector
15-Bit Latch
DATA
(13) Cntrl 19-Bit Shift Reg
Divider Output (fr/fp) MUX
(17) FOUT
CLOCK PWDN
(11) (19)
Pin Configuration
OSC_IN NC OSC_OUT VP VCC DO GND LD NC FIN 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 r PWDN p Fout BISW FC LE DATA NC CLOCK
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 February 2, 2000, rev. *A
WB1215
R5 Q1
Crystal Osc. Input 1000p
R4
(1) OSCIN
r
(20)
R6
Q2
(2) NC PWDN
(19)
(3) OSCOUT
100p
(18) p
R7 Q4 Q3
0.1
(4) VP VP FOUT
(17) R8 R9 Vp
0.1 100p
(5) VCC (6) DO FC VCC BISW
(16)
(15)
C1 C2 R2 C3 R3
(7) GND LE
(14)
(8) LD VP
VCO* 18 RFOUT VCC
(13) DATA
100k LD 33k 18 0.01 F 10k MMBT200 Lock Detect
(9) NC NC
(12)
(10) FIN CLOCK
(11)
18 50
100 pF
From Controller
Figure 1. Application Diagram Example - WB1215 1.2-GHz PLL
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WB1215
Pin Definitions
Pin Name OSC_IN NC OSC_OUT VP VCC DO GND LD NC FIN CLOCK NC DATA LE FC BISW FOUT
P
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
Pin Type I O P P O G O I I
Pin Description Oscillator Input: This input has a VCC/2 threshold and CMOS logic level sensitivity. No Connect Oscillator Output Charge Pump Rail Voltage: This supply for charge pump. Must be > VCC. Power Supply Connection for PLL: When power is removed from VCC all latched data is lost. Charge Pump Output: The phase detector gain is IP/2. Sense polarity can be reversed by setting FC LOW (pin 15). Analog and Digital Ground Connection: This pin must be grounded. Lock Detect Pin: This output is HIGH with narrow LOW pulses when the loop is locked. No Connect Input to Prescaler: Maximum frequency 1.2 GHz. Data Clock Input: One bit of data is loaded into the Shift Register on the rising edge of this signal. No Connect Serial Data Input Load Enable: On the rising edge of this signal, the data stored in the Shift Register is latched into the counters and configuration controls. Phase Sense Control for Phase Detector with Internal Pull-up: When pulled LOW, the polarity of the Phase Detector is reversed. Analog Switch Output: Connects to output of charge pump when LE is HIGH. Monitor Point for Phase Detector Input External Charge Pump Output: Open drain N-Channel FET, pull-up resistor required. Power Down Pin with Internal Pull-up: When pin is HIGH, device is in normal state. When pin is LOW, device is in power-down mode. When device enters power-down mode the charge pump is in the three-state condition. External Change Pump: (CMOS logic output).
I I I O O O I
PWDN
R
20
O
3
WB1215
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating Parameter VCC or VP VOUT IOUT TL TSTG Output Voltage Output Current Lead Temperature Storage Temperature Description Power Supply Voltage only. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Rating -0.5 to +6.5 -0.5 to V CC+0.5 15 +260 -55 to +150 Unit V V mA C C
Handling Precautions
Devices should be transported and stored in antistatic containers. These devices are static sensitive. Ensure that equipment and personnel contacting the devices are properly grounded. Cover workbenches with grounded conductive mats.
Always turn off power before adding or removing devices from system. Protect leads with a conductive sheet when handling or transporting PC boards with devices. If devices are removed from the moisture protective bags for more than 36 hours, they should be baked at 85C in a moisture free environment for 24 hours prior to assembly in less than 24 hours.
Recommended Operating Conditions
Parameter VCC VP TA Description Power Supply Voltage Charge Pump Voltage Operating Temperature Ambient air at 0 CFM flow Test Condition Rating 2.7 to 5.5 VCC to +5.5 -40 to +85 Unit V V C
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WB1215
Electrical Characteristics: VCC = 3.0V, VP = 3.0V, TA = -40C to +85C, Unless otherwise specified
Parameter ICC IPD FIN FOSC PFIN VOSC IIH, IIL VIH VIL IIH IIL VOH VOL IDO(SO) IDOH(SI) IDO Description Power Supply Current Power-down Current Maximum Operating Frequency Oscillator Input Frequency Input Sensitivity Oscillator Input Sensitivity Oscillator Input Current High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current High Level Output Voltage Low Level Output Voltage IDO, Source Current IDO High, Sink Current IDO Charge Pump Sink and Source Mismatch Charge Pump Current Variation vs. Temperature Charge Pump HighImpedance Leakage Current VP = 3.0V, VDO = V P/2 VP = 5.0V, VDO = V P/2 VP = 3.0V, VDO = V P/2 VP = 5.0V, VDO = V P/2 VD O = VP/2 [IIDO(SI)I - IIDO(SO)I]/ [1/2*{IIDO(SI)]I+IIDO(SO)I}]*100% -40CIDO vs T IDO-tri
5 2.5
% nA
Note: 1. IDOVS T; Charge pump current variation vs. temperature. [IIDO(SI)@T I - IIDO(SI)@25 CI]/IIDO(SI)@25CI * 100% and [IIDO(SO)@TI - IIDO(SO)@25CI]/IIDO(SO)@25CI *100%.
5
WB1215
Timing Waveforms
Phase Characteristics For normal operation, the FC pins is used to select the output polarity of the phase detector. Both the internal and any external charge pump are affected. Depending upon VCO characteristics, FC pin should be set accordingly: When VCO characteristics are like (1), FC should be set HIGH or OPEN CIRCUIT: When VCO characteristics are like (2), FC should be set LOW. When FC is set HIGH or OPEN CIRCUIT, Fout pin is set to the reference divider output, Fr. When FC is set LOW, Fout pin is set to the programmable divider output Fp.
VCO Input Voltage VCO Output Frequency
(1)
(2)
Phase Comparator Sense
Phase Detector Output Waveform
FR
FP tw tw
LD
DO Charge Pump Output Current Waveform
FR
FP tw tw
Do
IDO
Three-state
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WB1215
Timing Waveforms (continued)
Serial Data Input Timing Waveform[2, 3, 4, 5]
// DATA B11 = MSB B10 // B1 A7
// A1 // CNT = LSB
CLOCK // t1 LE // // t2 // t3 t5 t4
Serial Data Input
Data is input serially using the DATA, CLOCK, and LE pins. Two control bits direct data into the locations given in Table 1. Table 1. Control Configuration CNT 1 0 Function Reference Counter: R = 3 to 16383, set prescaler ratio PRE =0:128/129, PRE=1:64/65 Program Counter: A = 0 to 127, B = 3 to 2047
Table 2. Shift Register Configuration[6] 1 CNT 2 R1 3 R2 4 R3 5 R4 6 R5 7 R6 8 R7 9 R8 10 R9 11 R10 12 R11 13 R12 14 R13 15 R14 16 PRE 17 18 19 Reference Counter and Configuration Bits
Programmable Counter Bits CNT A1 A2 A3 A4 A5 A6 A7 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11
Bit(s) Name CNT R1-R14 PRE A1-A7 B1-B11
Function Control Bit: Directs programming data to reference or programmable counters. Reference Counter Setting Bits: 14 bits, R = 3 to 16383.[7] Prescaler Divide Bit: LOW = 128/129 and HIGH = 64/65. Swallow Counter Divide Ratio: A = 0 to 127. Programmable Counter Divide Ratio: B = 3 to 2047.[7]
Notes: 2. t1-t5 = 50 s > t > 0.5 s. 3. CLOCK may remain HIGH after latching in data. 4. DATA is shifted in with the MSB first. 5. For DATA definitions, refer to Table 2. 6. The MSB is loaded in first. 7. Low count ratios may violate frequency limits of the phase detector.
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WB1215
Table 3. 7-Bit Swallow Counter (A) Truth Table[8] Divide Ratio A 0 1 ::: 126 127 A7 0 0 ::: 1 1 A6 0 0 ::: 1 1 A5 0 0 ::: 1 1 A4 0 0 ::: 1 1 A3 0 0 ::: 1 1 A2 0 0 ::: 1 1 A1 0 1 ::: 0 1
Table 4. 11-Bit Programmable Counter (B) Truth Table[9] Divide Ratio B 3 4 ::: 2046 2047 B11 0 0 ::: 1 1 B10 0 0 ::: 1 1 B9 0 0 ::: 1 1 B8 0 0 ::: 1 1 B7 0 0 ::: 1 1 B6 0 0 ::: 1 1 B5 0 0 ::: 1 1 B4 0 0 ::: 1 1 B3 0 1 ::: 1 1 B2 1 0 ::: 1 1 B1 1 0 ::: 0 1
Table 5. 14-Bit Programmable Reference Counter Truth Table[9] Divide Ratio R 3 4 ::: 16382 16383 R14 0 0 ::: 1 1 R13 0 0 ::: 1 1 R12 0 0 ::: 1 1 R11 0 0 ::: 1 1 R10 0 0 ::: 1 1 R9 0 0 ::: 1 1 R8 0 0 ::: 1 1 R7 0 0 ::: 1 1 R6 0 0 ::: 1 1 R5 0 0 ::: 1 1 R4 0 0 ::: 1 1 R3 0 1 ::: 1 1 R2 1 0 ::: 1 1 R1 1 0 ::: 0 1
Ordering Information[10]
Ordering Code WB1215 Package Name X Package Type 20-pin TSSOP (0.173" wide) TR Tape and Reel Option
Notes: 8. B is greater than or equal to A. 9. Divide ratio less than 3 is prohibited. The divide ratio can be calculated using the following equation: fvco = {(P * B) + A} * fosc / R where (A < B) fvco: Output frequency of the external VCO. fosc: The crystal reference oscillator frequency. A: Preset divide ratio of the 7-bit swallow counter (0 to 127). B: Preset ratio of the 11-bit programmable counter (3 to 2047). P: Preset divide ratio of the dual modulus prescaler (64/65 or 128/129). R: Preset ratio of the 14-bit programmable reference counter (3 to 16383). The divide ratio N = (P * B) + A. 10. Operating temperature range: -40C to +85C.
Document #: 38-00865-A
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WB1215
Package Diagram
20-Pin Thin Shrink Small Outline Package (TSSOP, 0.173" wide)
Physical Dimensions In Millimeters 20 Lead (0.173" Wide) TSSOP Package Order Number X 20" clear antistatic tubes, 76 units/tube JEDEC Outline MO-153
(c) Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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